Cisco Ultra-low Latency Network Interface Card

High-density ultra-low latency

The Cisco Nexus^® X100 SmartNIC K3P-Q is a high-density NIC specifically optimized for low latency operation.

Features 2x QSFP28 ports that can be deployed in a high-density 8-channel configuration and software trigger-to-response latencies as low as 596ns. This is up to 20 percent faster than previous Cisco Nexus SmartNIC models making it one of the fastest high-density network adapter in the market. Users will find that this drop-in replacement NIC accelerates tick-to-trade performance to previously unachievable speeds increasing the efficacy and profitability of software-based trading systems.

Advanced software programmability

The Cisco Nexus X100 SmartNIC K3P-Q provides the most powerful programmable software interface on the market.

Programmability features include:

• Zero-latency cost hardware flow steering: allowing traffic filtering and steering to the right memory and CPU core with no latency penalty.
• Cut-through receive: This mechanism allows software to process packet fragments as they arrive from the wire while packet tails are still in flight. This is especially effective for slow line speeds (for example 1GbE). The Cisco Nexus X100 SmartNIC K3P-Q software API puts users well ahead of traditional store-and-forward NIC designs to make better decisions faster.
• ExaSOCK TCP/IP acceleration: Unmodified socket applications can benefit from the speed and power of the Cisco Nexus X100 SmartNIC K3P-Q using ExaSOCK. ExaSOCK is an in-place TCP/IP socket acceleration system. ExaSOCK's Extension API allows it to seamlessly interoperate with the X100 SmartNIC's transmit preloading feature described below.
• Preloaded packet transmit: The Cisco Nexus X100 SmartNIC K3P-Q allows users to preload transmit frames saving 60ns from the transmit path. The X100 SmartNIC K3P-Q features enlarged packet transmit buffers allowing many more frames to be preloaded leading to more versatile transmission choices.
• High-resolution timestamps: Four-nanosecond timestamps are applied to every received packet and the most recently transmitted packet. The Cisco Nexus X100 SmartNIC K3P-Q also features out of the box support for IEEE1588 (PTP) and high-speed capture to disk using free and open-source Exact-Capture software.

The Cisco Nexus X100 SmartNIC K3P-Q is a pure FPGA-based network adapter that is 25 ready.

Field Programmable Gare Array (FPGA) network adapters extend the useful life of the Cisco Nexus X100 SmartNIC K3P-Q by allowing new features and speed enhancements to be downloaded into the device after deployment. For example the X100 SmartNIC K3P-Q will support additional Ethernet speeds through a firmware update. This will reduce capital expenditure on lengthy and difficult infrastructure upgrades.

All-FPGA design

The Cisco Nexus X100 SmartNIC K3P-Q is built using the latest generation Xilinx UltraScale+ FPGA

It optionally ships with 9GB of DDR4 memory for custom use. It is a compact adapter in a low-profile form-factor. Users can benefit from the all-FPGA design by offloading critical network processing functions directly into the NIC while maintaining the ease of use and administration of a production-grade network adapter.

High-density ultra-low latency

The Cisco Nexus^® X100 SmartNIC K3P-Q is a high-density NIC specifically optimized for low latency operation.

Features 2x QSFP28 ports that can be deployed in a high-density 8-channel configuration and software trigger-to-response latencies as low as 596ns. This is up to 20 percent faster than previous Cisco Nexus SmartNIC models making it one of the fastest high-density network adapter in the market. Users will find that this drop-in replacement NIC accelerates tick-to-trade performance to previously unachievable speeds increasing the efficacy and profitability of software-based trading systems.

Advanced software programmability

The Cisco Nexus X100 SmartNIC K3P-Q provides the most powerful programmable software interface on the market.

Programmability features include:

• Zero-latency cost hardware flow steering: allowing traffic filtering and steering to the right memory and CPU core with no latency penalty.
• Cut-through receive: This mechanism allows software to process packet fragments as they arrive from the wire while packet tails are still in flight. This is especially effective for slow line speeds (for example 1GbE). The Cisco Nexus X100 SmartNIC K3P-Q software API puts users well ahead of traditional store-and-forward NIC designs to make better decisions faster.
• ExaSOCK TCP/IP acceleration: Unmodified socket applications can benefit from the speed and power of the Cisco Nexus X100 SmartNIC K3P-Q using ExaSOCK. ExaSOCK is an in-place TCP/IP socket acceleration system. ExaSOCK's Extension API allows it to seamlessly interoperate with the X100 SmartNIC's transmit preloading feature described below.
• Preloaded packet transmit: The Cisco Nexus X100 SmartNIC K3P-Q allows users to preload transmit frames saving 60ns from the transmit path. The X100 SmartNIC K3P-Q features enlarged packet transmit buffers allowing many more frames to be preloaded leading to more versatile transmission choices.
• High-resolution timestamps: Four-nanosecond timestamps are applied to every received packet and the most recently transmitted packet. The Cisco Nexus X100 SmartNIC K3P-Q also features out of the box support for IEEE1588 (PTP) and high-speed capture to disk using free and open-source Exact-Capture software.

The Cisco Nexus X100 SmartNIC K3P-Q is a pure FPGA-based network adapter that is 25 ready.

Field Programmable Gare Array (FPGA) network adapters extend the useful life of the Cisco Nexus X100 SmartNIC K3P-Q by allowing new features and speed enhancements to be downloaded into the device after deployment. For example the X100 SmartNIC K3P-Q will support additional Ethernet speeds through a firmware update. This will reduce capital expenditure on lengthy and difficult infrastructure upgrades.

All-FPGA design

The Cisco Nexus X100 SmartNIC K3P-Q is built using the latest generation Xilinx UltraScale+ FPGA

It optionally ships with 9GB of DDR4 memory for custom use. It is a compact adapter in a low-profile form-factor. Users can benefit from the all-FPGA design by offloading critical network processing functions directly into the NIC while maintaining the ease of use and administration of a production-grade network adapter.